A finite state machine is a machine that have state, change of state and output. The example is a moore machine or a mearly machine.

A Finite State Machine (FSM) is a mathematical model of computation used to design sequential logic.

It consists of:

• States → The machine’s memory of past behavior.
• Transitions → Rules that determine how the machine moves from one state to another based on inputs.
• Outputs → The result produced depending on the current state (and sometimes the input).

FSMs are widely used in digital design, protocols, and control systems.

Types of FSMs

1. Moore Machine

• Output depends only on the current state.
• More stable, as output does not change immediately with input.
• Typically requires more states compared to Mealy.

Output Function:

Output=f(State)Output = f(State)

Output=f(State)

2. Mealy Machine

• Output depends on both current state and input.
• Can react faster to inputs.
• Often requires fewer states than Moore.

Output Function:

$Output=f(State,Input)Output=f(State,Input)$

General FSM Block Diagram

          +----------+
 Input -->|  Next    |--> State
          | State    |
          | Logic    |
          +----------+
               |
               v
          +----------+
          |  State   |
          | Register |
          +----------+
               |
               v
          +----------+
          | Output   |
          | Logic    |
          +----------+
               |
             Output

FSM in Verilog

FSMs in Verilog are usually described in three parts:

1. State Register → Holds the current state.
2. Next State Logic → Determines the next state.
3. Output Logic → Generates outputs.

Example: Simple Moore FSM

module moore_fsm (
    input clk, reset, in,
    output reg out
);
    // State encoding
    typedef enum reg [1:0] {
        S0 = 2'b00,
        S1 = 2'b01,
        S2 = 2'b10
    } state_t;

    state_t current_state, next_state;

    // State register
    always @(posedge clk or negedge reset) begin
        if (!reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            S0: next_state = in ? S1 : S0;
            S1: next_state = in ? S2 : S0;
            S2: next_state = in ? S2 : S0;
            default: next_state = S0;
        endcase
    end

    // Output logic (Moore → depends only on state)
    always @(*) begin
        case (current_state)
            S0: out = 0;
            S1: out = 0;
            S2: out = 1;
            default: out = 0;
        endcase
    end
endmodule