Verilog Implementation

module S_Reg (
    input clk, reset, SW, PS, Sin,
    input [7:0] Pin,       // Parallel input data
    output Sout,           // Serial output (MSB)
    output [7:0] Pout      // Parallel output (entire register)
);

    reg [7:0] SReg;

    always @(posedge clk or negedge reset) begin
        if (!reset) begin
            SReg <= 8'd0;
        end
        else if (SW) begin
            // Rotate left when shift mode is enabled
            SReg <= {SReg[6:0], SReg[7]};
        end
        else begin
            if (!PS) begin
                // Serial input mode
                SReg <= {SReg[6:0], Sin};
            end
            else begin
                // Parallel load mode
                SReg <= Pin;
            end
        end
    end

    assign Sout = SReg[7];  // MSB as serial output
    assign Pout = SReg;     // Entire register as parallel output

endmodule

With Denounce Circuit (To see increment when button pressed)

module SR_display(
    input reset, btn, clk, Sin, SW, PS,
    input [7:0] Pin,
    output Sout,
    output [6:0] Seg0, Seg1
);

    wire SR_clk;     // Clean clock pulse from debounce
    wire [7:0] Pout; // Parallel output from shift register

    // Debounce the button to generate a clean clock pulse
    Debounce_Circuit DC0(
        .Din(btn),
        .clk(clk),
        .reset(reset),
        .Dout(SR_clk)
    );

    // Instantiate shift register with debounced clock
    S_Reg S_Reg_0(
        .clk(SR_clk),
        .reset(reset),
        .SW(SW),
        .PS(PS),
        .Sin(Sin),
        .Pin(Pin),
        .Sout(Sout),
        .Pout(Pout)
    );

    // Display contents of shift register on two 7-segment displays
    Seven_Segment SS0(.Din(Pout[3:0]), .Dout(Seg0)); // Lower nibble
    Seven_Segment SS1(.Din(Pout[7:4]), .Dout(Seg1)); // Upper nibble

endmodule