A Full Adder is a fundamental combinational circuit used to add three inputs (A, B, and C_in) and produce:

• Sum: The binary sum of the inputs.
• C_out: The carry output.

Truth Table

Karnaugh Maps (K-Maps)

C_out

Simplified Expression:
$C_{\text{out}}=(A\cdot B)+(B\cdot C_{\text{in}})+(A\cdot C_{\text{in}})$

Sum

Simplified Expression:
$\text{Sum}=A\oplus B\oplus C_{\text{in}}$

Verilog Implementations

1. General Full Adder

module FA(A, B, C_in, Sum, C_out);
    input A, B, C_in;
    output Sum, C_out;

    // Gate-Level Modeling for Sum
    xor X1(Sum, A, B, C_in);

    // Data-Flow Modeling for Carry
    assign C_out = (A & B) | (B & C_in) | (A & C_in);

endmodule

2. Full Adder with Generate and Propagate (Used in 4-Bit Carry-Lookahead Adder)

module FACLA4(A, B, C_in, G, P, S);
    input A, B, C_in;
    output G, P, S;

    assign S = A ^ B ^ C_in;  // Sum
    assign G = A & B;         // Generate
    assign P = A | B;         // Propagate
endmodule