Carry-Lookahead Generator

A Carry-Lookahead Generator is used in a Carry-Lookahead Adder (CLA) to significantly improve speed.
Unlike a Ripple-Carry Adder (RCA), which computes each carry sequentially, the CLG calculates all carry signals simultaneously from the inputs, reducing propagation delay.

Concept and Derivation

Define:
- Carry Generate:
  $G_{i} = A_{i} \cdot B_{i}$
  (A carry is generated when both inputs are 1.)
- Carry Propagate:
  $P_{i} = A_{i} + B_{i}$
  (A carry will propagate through if at least one input is 1.)
The general formula for carry:
$C_{i} = G_{i} + (P_{i} \cdot C_{i - 1})$

Example for 4-Bit CLA

For a 4-bit Carry-Lookahead Adder, the carries are:

$C_{0} = G_{0} + P_{0} C_{i n}$
$C_{1} = G_{1} + P_{1} C_{0} = G_{1} + P_{1} G_{0} + P_{1} P_{0} C_{i n}$
$C_{2} = G_{2} + P_{2} G_{1} + P_{2} P_{1} G_{0} + P_{2} P_{1} P_{0} C_{i n}$
$C_{o u t} = G_{3} + P_{3} G_{2} + P_{3} P_{2} G_{1} + P_{3} P_{2} P_{1} G_{0} + P_{3} P_{2} P_{1} P_{0} C_{i n}$

This allows parallel computation of all carries, avoiding ripple delay.

Verilog Implementation

module CLG(G, P, C, C_in, C_out);
input  [3:0] G, P;
input        C_in;
output [2:0] C;
output       C_out;

// Carry outputs based on carry-lookahead logic
assign C[0] = G[0] | (P[0] & C_in);

assign C[1] = G[1] |
              (P[1] & G[0]) |
              (P[1] & P[0] & C_in);

assign C[2] = G[2] |
              (P[2] & G[1]) |
              (P[2] & P[1] & G[0]) |
              (P[2] & P[1] & P[0] & C_in);

assign C_out = G[3] |
              (P[3] & G[2]) |
              (P[3] & P[2] & G[1]) |
              (P[3] & P[2] & P[1] & G[0]) |
              (P[3] & P[2] & P[1] & P[0] & C_in);

endmodule