A 4-bit multiplier operates similarly to manual multiplication, but in binary.
For two 4-bit numbers A and B, the process involves:

• Generating 4 partial products using the Multiplier Unit
• Adding them sequentially using Carry-Lookahead Adders (CLA4)
• This results in an 8-bit product.

Block Diagram

Verilog Implementation

module Multiplier4(A, B, P);
    input [3:0] A, B;
    output [7:0] P;

    wire [3:0] MUout0, MUout1, MUout2, MUout3;
    wire [3:0] S0, S1;
    wire CLAout0, CLAout1;

    // Partial products
    MultiplierUnit MU0(.A(A), .B(B[0]), .MUout(MUout0));
    MultiplierUnit MU1(.A(A), .B(B[1]), .MUout(MUout1));
    MultiplierUnit MU2(.A(A), .B(B[2]), .MUout(MUout2));
    MultiplierUnit MU3(.A(A), .B(B[3]), .MUout(MUout3));

    // First CLA
    CLA4 CLA0(
        .C_in(1'b0),
        .A({1'b0, MUout0[3:1]}),
        .B(MUout1),
        .S(S0),
        .C_out(CLAout0)
    );

    // Second CLA
    CLA4 CLA1(
        .C_in(1'b0),
        .A({CLAout0, S0[3:1]}),
        .B(MUout2),
        .S(S1),
        .C_out(CLAout1)
    );

    // Third CLA
    CLA4 CLA2(
        .C_in(1'b0),
        .A({CLAout1, S1[3:1]}),
        .B(MUout3),
        .S(P[6:3]),
        .C_out(P[7])
    );

    // Output bits
    assign P[0] = MUout0[0];
    assign P[1] = S0[0];
    assign P[2] = S1[0];
endmodule