In Verilog, numbers are declared in the following format:
<number of bits>'<number system><value>

Components

<number of bits>'<number system><value>

• <number of bits> → The bit width of the number (integer)
• • <number system>:
    • b → Binary
    • o → Octal
    • d → Decimal
    • h → Hexadecimal
• <value> → The actual value in the given number system

Examples

1. Binary
   3'b101

   • Bit width: 3
   • Number system: Binary
   • Value: 101₂ = 5 (decimal)

2. Decimal
   11'd9

   • Bit width: 11
   • Number system: Decimal
   • Value: 9 (stored in 11 bits)

3. Hexadecimal
   12'h3ac

   • Bit width: 12
   • Number system: Hexadecimal
   • Value: 3AC₁₆ = 940 (decimal)