IO & Config Writes

A posted write (like a normal PCIe Memory Write) just sends the data and does not wait for a reply.
A non-posted write sends the data and waits for a Completion TLP confirming it was successfully received.

These types of writes often change device state or control registers.
The system must guarantee that the write was actually received before proceeding to the next step.
If it were just posted (fire-and-forget), software might:
- Move to the next operation too early.
- Miss an error that happened during the write.
- Cause race conditions or inconsistent device states.

CPU (Root Port) Sends IO/Config Write Request
- Targets a specific IO space or configuration space address.
- Routed through switches based on IO address.
Target Endpoint Receives the Request
- Accepts the data and updates its IO/config register.
Target Sends Completion TLP
- No data payload (just a status).
- Confirms success or reports an error in the status field.
Requester (CPU) Waits
- Only after receiving a successful completion does software proceed to the next step.

Feature	Memory Write (Posted)	IO/Config Write (Non-Posted)
Waits for Completion?	❌ No	✅ Yes
Performance	✅ Faster (no waiting)	⏳ Slower (must wait for reply)
Error Reporting	❌ No feedback unless later error handling kicks in	✅ Immediate (via completion status)
Use Case	Bulk data transfer to memory	Device control, register programming, critical sequences

IO space and Configuration cycles are legacy PCI concepts.
PCIe retains support for backward compatibility but encourages Memory-Mapped I/O (MMIO) instead, where device registers are accessed via memory writes (posted transactions).
Modern PCIe devices generally don’t use IO space at all.