So instead, PCIe uses a source-synchronous model:

• The transmitter (TX) sends data and “hides” the clock inside the data stream.
• The receiver (RX) extracts the clock from the data stream so it knows exactly when to sample the bits.

Embed the Clock in the Data

PCIe transmits data using 8b/10b encoding (for Gen1/Gen2 — later generations use other schemes).

• This encoding adds extra bits to the data in a way that ensures:
  • Enough transitions (0→1 or 1→0) occur in the bitstream.
  • DC balance (equal number of 1s and 0s) is maintained.

These transitions let the receiver figure out the timing of the incoming bits.

Clock Recovery: How the Receiver Gets the Timing

Inside the receiver is a PLL (Phase-Locked Loop):

1. The PLL looks at the incoming bit stream.
2. It generates its own local clock and compares its phase to the data transitions.
3. It speeds up or slows down its clock until its edges line up with the transitions in the data.
4. Once synchronized, we say the PLL is locked — now it can correctly “sample” the incoming bits.

This process happens continuously — so if the transmitter clock drifts slightly due to temperature or voltage changes, the PLL tracks it.

Why 8b/10b Encoding is Important

If there were too many consecutive 1s or 0s (no transitions), the PLL would lose synchronization and start drifting.

8b/10b prevents this by guaranteeing at least one transition every 5 bits, so the PLL always has something to “lock” onto.

Why the Recovered Clock Isn’t Used for Everything

Students often ask:

“Why not use the recovered clock to run the entire receiver logic?”

Answer:

• When the PCIe link goes into low-power states, data stops being transmitted.
• No data → no transitions → PLL can’t generate a valid clock.
• The receiver still needs its own local reference clock to keep working and wake up when data resumes.

So, the recovered clock is used only for sampling incoming data, not for driving the whole chip.