• Not officially a PCIe layer – but it’s the reason PCIe exists (it generates or consumes the actual data).
• Think of it as the application logic of the device:
  • For a NIC → this is where packets are queued, filtered, DMA’d.
  • For an SSD → this is where flash translation, wear leveling, and queue management happen.
  • For a GPU → this is where shaders, command processors, and memory controllers live.

🔼 Transmit Side

The Device Core gives the Transaction Layer:

• Transaction type: (Read, Write, Message, Completion)
• Address: Target memory or register address
• Length: Amount of data
• Attributes: Ordering, priority, relaxed ordering flags, etc.

The Transaction Layer then packages this into a TLP and sends it down the stack.

🔽 Receive Side

When packets arrive from PCIe:

• The Transaction Layer strips off headers, decodes the meaning, and hands the payload up to the device core.
• The core interprets it (e.g. “host just wrote to this register” or “here’s the data you requested”) and updates its internal logic or DMA engines.

🗣 Why Call it "Software Layer"?

• It is logically equivalent to software drivers in the host — it tells the PCIe interface what to do.
• It’s just that here, it’s implemented in hardware/firmware inside the device.
• The PCIe spec doesn’t define what this logic must look like — it’s vendor-specific.