PCI Bus Device Limits (Explained Simply)

• Theoretical limit: PCI can support up to 32 devices per bus.
• Practical limit: At 33 MHz, only about 10–12 electrical loads can be used reliably.

Why the limit exists

PCI uses reflected-wave signalling to save power and cost:

1. Weak drivers: Devices don’t fully drive the signal (only about half the required voltage).
2. Signal travels: The partial signal moves down the bus trace.
3. Reflection: At the end of the trace, there’s no termination. The signal reflects back.
4. Full voltage: The reflection adds to the original wave, creating the full signal level.
5. Termination: When the reflected signal returns to the transmitter, the driver (part of initiator) absorbs it (stopping further reflections).

Timing requirement

• The total delay =

  • Time for the signal to travel down the wire,
  • • Time for the reflection to return,
  • • Setup time at the receiver.

• This total delay must be less than one clock cycle (at 33 MHz ≈ 30 ns).

Effect of bus length and devices

• Longer traces + more devices = longer round-trip time.
• At 33 MHz, this restricts the bus to 10–12 electrical loads max.

Electrical load definition

• One load = one device on the motherboard.
• One connector slot = two loads (because it adds capacitance and stubs).
• Result: a 33 MHz PCI bus can support only 4–5 add-in slots (plus onboard devices).