Each D-PHY Link consists of a Master side and a Slave side:

• The Master:

  • Generates and sends the High-Speed DDR clock through the Clock Lane
  • Acts as the main data source

• The Slave:

  • Receives the clock from the Clock Lane
  • Acts as the main data sink

Data Direction

• The Forward Direction refers to data flowing from Master → Slave.
• The Reverse Direction refers to data flowing from Slave → Master.

Reverse-direction transmission is only available on Bi-directional Data Lanes.

Clock Lane Direction

• The Clock Lane is always unidirectional and always operates Master → Slave, regardless of data direction.

Reversible Data Lanes

• When Data Lanes are configured as Bi-directional, they may be dynamically turned around so that the Slave becomes the data source as needed.