The Clock Lane is special. Unlike Data Lanes, it only sends the High-Speed DDR Clock from the Master to the Slave.
Required Functions for Each Side
| Lane Side | Required Blocks | Optional |
|---|---|---|
| Master Side | HS-TX, LP-TX, CIL-MCNN |
ALP-ED |
| Slave Side | HS-RX, LP-RX, CIL-SCNN |
ALP-ED |
| Even though it is used only for clock signals, it still requires High-Speed and Low-Power transmit/receive blocks like a unidirectional data lane. |
How Clock Lanes Differ from Data Lanes
Even though Clock Lanes look similar, they are not identical to Unidirectional Data Lanes. Key differences:
1. Clock is sent in quadrature phase
- The High-Speed DDR Clock is 90° out of phase with the data signals
- (Instead of “in-phase” like normal data)
This helps receivers sample data correctly.
2. Escape Mode entry works differently
- Data Lanes use special "Escape Mode entry codes"
- Clock Lanes do NOT
- Clock Lanes only need to enter ULPS (Ultra-Low Power State)
3. Clock Lane only supports ULPS
- No LPDT (Low-Power Data Transmission)
- No other Escape Mode features
Clock Signals Are Generated Outside the PHY
- The high-frequency internal clock source is not part of the D-PHY itself
- A Clock Generation Unit (e.g., a PLL multiplier) creates clocks with special phases
- These clock phases must be high-quality to pass all timing rules.
The specification does not define how to build that clock generator.