This design pattern creates a one-clock-cycle-wide pulse in the receiving clock domain,
which serves as a precise strobe signal to capture multi-bit data that has crossed clock domains.

🕹️ The Core Idea

Instead of sending a level signal that must be stretched long enough to be detected,
we send a toggling signal (a single bit that flips state every time a new data word is ready).

This toggle passes through a 3-stage synchronizer in the receiving domain,
and by comparing two consecutive synchronization stages (using an XOR gate),
a one-cycle pulse is generated whenever a toggle change is detected.

This pulse acts as a safe “capture now” command for the destination logic.

⚙️ Circuit Breakdown

Let’s denote:

• d → toggle signal from source clock domain
• q1, q2, q3 → 3 flip-flops in the synchronizer chain, clocked by the destination clock
• sync_pulse → one-clock-cycle-wide output pulse
• q3 → synchronized version of the input (delayed by three cycles)

Verilog-like description:

always @(posedge dest_clk) begin
    q1 <= d;          // 1st synchronizer stage
    q2 <= q1;         // 2nd stage
    q3 <= q2;         // 3rd stage
end

assign sync_pulse = q2 ^ q3;  // XOR detects any change (toggle edge)
assign q_out = q3;            // Delayed version of input

🧠 How It Works — Step-by-Step

Let’s follow the operation through cycles:

1. Cycle 1 — Source toggles d high (new data ready).
2. Cycle 2–4 — The high value propagates through the synchronizer stages (q1, q2, q3).
3. When q2 and q3 temporarily differ (e.g., q2=1, q3=0),
   their XOR output = 1, generating a 1-cycle pulse in the destination domain.
4. This pulse (sync_pulse) signals capture the data now.
5. Cycle 7 — Source toggles d low (next data ready).
   Again, after synchronization delay, another 1-cycle pulse appears.
6. The q_out follows the toggle state delayed by three destination clock cycles,
   which can be used for feedback/acknowledge back to the source domain.

🧩 Key Features

✅ Advantages

• Safe and simple — uses standard flip-flop synchronizers and XOR logic.
• Detects both edges — no need to worry about high/low polarity.
• Perfect for handshaking — the q_out feedback can be sent back through another identical synchronizer in the opposite direction.
• Guaranteed 1-cycle pulse width — easy for destination logic to use as a strobe signal.

⚠️ Design Requirements

• The receiving domain must capture the data during the same cycle that the pulse occurs.
• The pulse exists for only one destination clock cycle, so downstream logic must be ready to use it immediately.
• The data bus must be stable before the pulse occurs and must remain stable for at least the entire receiving clock cycle when the pulse is active.

🪄 Typical Usage Pattern

This synchronized enable pulse circuit forms the heart of many reliable CDC handshaking systems.

• Forward path:
  Source → toggle bit → synchronizer → XOR pulse → destination captures data.
• Return path (optional):
  Destination’s q_out → synchronized back → source sees acknowledgment.
  This allows both open-loop (no feedback) and closed-loop (feedback-based) MCP communication.

📊 Summary Table

🧩 Why It’s Preferred

This technique ensures that:

• You never rely on absolute timing between clock domains.
• Every new data toggle produces exactly one capture pulse.
• Metastability risk is confined to the synchronizer and is statistically negligible with 3 stages.